A standard event status register is an 8-bit register.

If even one of the standard status byte register bits enabled by the standard event status enable register becomes "1", bit 5 (ESB) of the status byte register becomes 1.

See: Standard Event Status Enable Register

The content of the standard event register is cleared at the following times.

• The *CLS command is executed.
• An event register query is executed. (*ESR?).
• The power is turned on again.

When the standard event status enable register is used to set each of the bits to "1" the corresponding bits are enabled in the standard event status register.

Standard Event Status Register (SESR) and Standard Event Status Enable Register (SESER)

Four event status registers have been provided for managing events in the unit.

An event status register is an 8-bit register.

If even one of the event status register bits enabled by the event status enable register becomes "1" the corresponding bit becomes as follows.

• When event status register 0: Bit 0 (ESB0) of the status byte register becomes "1"
• When event status register 1: bit 1 (ESB1) becomes "1"
• When event status register 2: bit 2 (ESB2) becomes "1"
• When event status register 3: bit 3 (ESB3) becomes "1"

The content of event status register 0, 1, 2, and 3 is cleared at the following times.

• The "*CLS" command is executed.
• An event status register query is executed ( :ESR0?, :ESR1?, :ESR2?, :ESR3? )
• The power is turned on again.

Event Status Register 0 (ESR0), 1 (ESR1), 2 (ESR2), and 3 (ESR3) and

Event Status Enable Register 0 (ESER0), 1 (ESER1), 2 (ESER2), and 3 (ESER3)

The following commands can be used by interface functions.